ON THE DESIGN OF VLSI CIRCUITS FOR THE WINOGRAD FOURIER TRANSFORM ALGORITHM

Authors
  1. Lavoie, P.
  2. Martineau, S.
Corporate Authors
Defence Research Establishment Ottawa, Ottawa ONT (CAN)
Abstract
A VLSI architecture for computing the discrete Fourier transform (DFT) using the Winograd Fourier transform algorithm (WFTA) is presented. This architecture is an addressless, routed, bit-serial scheme that directly maps an N-point algorithm onto silicon. The architecture appears to be far less costly than systolic schemes for implementing the WFTA, and faster than current FFT devices for similar transform sizes. The nesting method of Winograd is used for partitioning larger transformations into several circuits. The advantage of this partitioning technique is that it allows using circuits that are all of the same type. However, the number of input/output pins of each circuit is higher than with some other approaches like, for example, the prime factor algorithm. The design of a 20-point DFT circuit with logic diagrams of its major cells is presented. TRUNCATED
Report Number
DREO-1108 —
Date of publication
15 Dec 1991
Number of Pages
84
DSTKIM No
92-00836
CANDIS No
103730
Format(s):
Hardcopy;Originator's fiche received by DSIS

Permanent link

Document 1 of 1

Date modified: