UTILIZATION OF AN ELECTRONIC CIRCUIT SIMULATOR IN CMOS LATCH-UP STUDIES

Authors
  1. Varga, L.
Corporate Authors
Defence Research Establishment Ottawa, Ottawa ONT (CAN)
Abstract
The 2-D device simulator presented allows the effect of radiation dose rate on the performance of CMOS circuits to be investigated. The simulator is composed of two parts, a diffusion current module and a lumped-element module. The first module, solves the current transport equations with the aid of the HSPICE code. The lumped-element module then simulates the electrical characteristics of the parasitic pnpn structure (present in CMOS circuits) using the results from the first module as input parameters. The model was applied to study the latch-up vulnerability of a CMOS inverter as a function of circuit layout and distribution of substrate contacts. Results of radiation hardening efforts are presented.
Report Number
DREO-1144 —
Date of publication
01 Jun 1992
Number of Pages
44
DSTKIM No
93-00463
CANDIS No
127945
Format(s):
Hardcopy;Originator's fiche received by DSIS

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