SPEEDING UP COMMUNICATIONS IN LARGE PARALLEL SYSTEMS IN A ULSI CONTEXT

Authors
  1. Audet, D.
  2. Savaria, Y.
  3. Arel, N.
Corporate Authors
Quebec Univ, Chicoutimi QUE (CAN) Computer Engineering Dept;Ecole Polytechnique, Montreal QUE (CAN) Dept of Electrical Engineering;Chief of Research and Development, Ottawa ONT (CAN) Director of Research and Development Communications and Space
Abstract
A simple and very effective solution to the delay incurred while propagating signals through long interconnection wires (such as those found in large parallel systems) is presented. The basic idea of the technique relies on the fragmentation of the wires and in reconnecting them with a special device in order to form a bidirectional pipeline. A method for determining the optimum configuration of the pipeline is presented. It is shown that, for a 10cm 8-bit bus implemented in a 1,2 mu m CMOS technology, the technique improves the transmission speed by more than 150% for 32-byte messages. The improvement increases for longer messages. It is also shown that the actual transmission time is close (to within a factor of 2) to the theoretical limit that could be achieved with a zero-length wire. A VLSI implementation of the reconnection device is also described.
Date of publication
01 Jan 1992
Number of Pages
19
DSTKIM No
93-03613
CANDIS No
128591
Format(s):
Hardcopy;Originator's fiche received by DSIS

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