EFFECTIVE ULTRA LARGE SCALE INTEGRATION (ULSI) ARCHITECTURE TECHNIQUES: THE HOST INTERFACE

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Authors
  1. Arel, N.
  2. Laperle, F.
  3. Savaria, Y.
  4. Audet, D.
Corporate Authors
Chief of Research and Development, Ottawa ONT (CAN) Director of Research and Development Communications and Space;Ecole Polytechnique, Montreal QUE (CAN) Centre de Developpement Technologique
Abstract
This document is intended to give a detailed description of the host interface. However, to have a more global view of the proposed system, please refer to (AUD94). The host interface is the communication bridge between the host system and a type N router (ARE95), and this router is the main link to the proposed parallel communication system. In the future, the combination of this interface and a type N router could become a new optimized component called a type M (Master) router as described in the original project proposal. The main objective of the interface is to simplify the communication between the host system and the router communication network. Since the nature and timing requirements of the host system and the router communication network are utterly different, an asynchronous mechanism was devised to interface both systems. Two memory units are utilized for buffering incoming and outgoing communications. Currently, the reception of messages coming from the router network is achieved using a dual-port 1 kbyte memory unit (reception memory unit). The other memory unit is used to store messages sent to the router network. It is a single-port memory having a capacity of 64 kbytes (send memory unit). Finally, the kernel of host interface was implemented using a Xilinx XC3090 FPGA component and support circuitry.
Keywords
VLSI;ULSI;Ultra Large Scale Integration
Report Number
P1348.4-6 —
Date of publication
01 Mar 1995
Number of Pages
58
DSTKIM No
96-02300
CANDIS No
497170
Format(s):
Document Image stored on Optical Disk;Hardcopy

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