IMPLEMENTATION OF A DIGITAL PHASE-LOCKED LOOP ON A VECTOR PROCESSOR

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Authors
  1. Maranda, B.H.
Corporate Authors
Defence Research Establishment Atlantic, Dartmouth NS (CAN)
Abstract
A digitial phase-locked loop (DPLL) has been implemented as part of a demodulator that reproduces data signals telemetered over a radio link. This paper describes the design of the DPLL and its implementation on a vector-processing card for real-time operation; also described is the automatic gain control (AGC) placed in front of the DPLL.
Keywords
Digital phase locked loop (DPLL)
Date of publication
01 Sep 1997
Number of Pages
7
DSTKIM No
98-00096
CANDIS No
506667
Format(s):
Hardcopy;Document Image stored on Optical Disk

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