GROUND TERMINAL PROCESSOR INTERFACE BOARD FOR SKYNET UPLINK SYNCHRONIZATION TRIALS

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Authors
  1. Tom, C.
Corporate Authors
Defence Research Establishment Ottawa, Ottawa ONT (CAN)
Abstract
A ground terminal (GT) simulator subsystem is being developed at Defence Research Establishment Ottawa (DREO) as part of the in-house work examining the aspects of uplink synchronization for extremely-high-frequency (EHF) spread spectrum satellite communications (SATCOM). Requirements of the GT subsystem include the generation of hop clock and data clock signals, and the interface between the GT processor and a hopping synthesizer controller (HSC) for commanding the HSC and transmitting data. A GT processor interface (i/f) board was designed and fabricated at DREO to satisfy these requirements. This report decribes the functions of the i/f board and specific requirements related to the uplink synchronization experiments and the interface to the HSC. The i/f board is a printed circuit board which is contained in a backplane chassis and is driven by the GT processor. The GT processor is realized by a Spectrum Signal Processing Inc. TMS320C30 digital signal processor board and communicates with the GT processor i/f board via the DSPLINK interface through the backplane. This report includes implementation details of the clock generation and interface circuitry and a user's guide for the proper configuration, installation and operation of the GT processor i/f board.
Keywords
SKYNET 4A;Uplinks;Clock generation;Ground Terminal Simulator Interface Board
Report Number
DREO-1321 — Technical report
Date of publication
01 Nov 1997
Number of Pages
61
DSTKIM No
98-00450
CANDIS No
507095
Format(s):
Hardcopy;Document Image stored on Optical Disk

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