SIDE-LOBE CANCELLER IF RECEIVER DESIGN

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Authors
  1. Curnow, J.
Corporate Authors
Defence Research Establishment Ottawa, Ottawa ONT (CAN);Applied Silicon Inc Canada, Ottawa ONT (CAN)
Abstract
This report is the final design report for the Side-Lobe Canceller (SLC) 60 megahertz IF receiver system. It presents the detailed designs and calculations for each section of the IF receiver. Numerous diagrams are used and the three page schematic diagram is included as an appendix. This report presents the design before final prototype testing, therefore the design is subject to minor changes following testing. The Side-Lobe Controller IF receiver consists of a series of eight identical boards, one for each channel of the SLC array. Each board is capable of producing one I and one Q output at a level that is suitable for digitizing by a data acquisition system. In addition, the boards provide monitor points and a high level 60 MHz output, suitable for future digital sampling. Each board also has an offset video output, with a bandwidth of one to six megahertz. The receiver enclosure is mounted in a rack in the portable laboratory, close to the data acquisition systems its outputs are connected to. The eight channel receiver boards are mounted in a double height eurocard rack, with a ninth board for the computer interface, reference amplifier and splitter. All IF and video connections are made at the rear of the enclosure, with a backplane assembly for power and control signals.
Keywords
Side Lobe Canceller (SLC);IF Receiver;Intermediate frequencies;Noise figure;Offset Video;Digital attenuator;Quadrature Phase Detector;Besslel Low Pass Filter;Sallen-Key Filter Circuit;Voltage Variable Phase Shifter (VVPS)
Report Number
DREO-CR-98-618;ASIC-50071 — Contractor Report; Technical Report (Final)
Date of publication
30 Apr 1993
Number of Pages
107
DSTKIM No
98-02239
CANDIS No
508983
Format(s):
Hardcopy;Document Image stored on Optical Disk

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