RTL Design of a Generic Pseudonoise Generator

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Authors
  1. Beaumont, J-F.
Corporate Authors
Defence R&D Canada - Ottawa, Ottawa ONT (CAN)
Abstract
Pseudonoise (PN) generators have many applications in the field of digital signal processing, especially in wireless communication systems. They are usually implemented in hardware through the use of Linear Feedback Shift Registers (LFSR) in either Application Specific Integrated Circuits (ASICs), Field Programmable Gate Array (FPGAs) or Complex Programmable Logic Devices (CPLDs). Although the methods and techniques to code the Register Transfer Level (RTL) algorithm with a Hardware Description Language (HDL) are currently well known in the design community, this technical memorandum presents an innovative code implementation. This new algorithm is a generic PN generator that takes as input the polynomial and its associated degree and, using current synthesis tools, generates a compact area circuit. Results show that the generated circuit does not consume more logic resources than a traditional hardcoded PN generator. The net advantage of using this new algorithm over its predecessor is significant savings in terms of design time, verification time and hence, development costs.

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Report Number
DRDC-OTTAWA-TM-2004-176 — Technical Memorandum
Date of publication
01 Sep 2004
Number of Pages
36
DSTKIM No
CA025164
CANDIS No
522715
Format(s):
CD ROM

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