DESIGN OF A PARALLEL SIGNAL PROCESSING ARCHITECTURE FOR ESM

Authors
  1. Hickman, L.
Corporate Authors
Carleton Univ, Ottawa ONT (CAN) Dept of Systems and Computer Engineering;Defence Research Establishment Ottawa, Ottawa ONT (CAN)
Abstract
The thesis presents a three stage parallel processing architecture for an ESM subprocessing system. The system architecture reflects the ESM system processing functions, namely emitter detection, emitter identification and emitter tracking. It is modular and expandable to meet the needs of today's rapidly changing ESM environment. Incorporated in the system design is a dedicated front-end processing section, which distributes the input data to the following processing stages. With input data rates to ESM systems becoming increasingly high, this is needed to reduce the subsequent data rates to a manageable level. Also, included in the design is the use of a commercially available digital signal processor for the purpose of emitter tracking in real-time. First, the system architecture is presented to hardware board level. Second, the system functions requiring dedicated hardware designs are identified and the designs presented.
Report Number
ARTT-87-6 — Contractor Report; Thesis; Advanced Real-time Toolset for Computer Systems Engineering Report
Date of publication
15 Mar 1987
Number of Pages
147 (some del)
DSTKIM No
87-03668
CANDIS No
52456
Format(s):
Hardcopy;Originator's fiche received by DSIS

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