A reduced-complexity lookup table approach to solving mathematical functions in FPGAs

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Authors
  1. Low, M.
  2. Lee, J.P.Y.
Corporate Authors
Defence R&D Canada - Ottawa, Ottawa ONT (CAN)
Abstract
Certain mathematical functions, such as the inverse, log, and arctangent, have traditionally been implemented in the digital domain using the Coordinate Rotation Digital Computer (CORDIC) algorithm. In this study, it is shown that it is possible to achieve a similar degree of numerical accuracy using a reduced-complexity lookup table (RCLT) algorithm, which is much less computationally-intensive than the CORDIC. On programmable digital signal processor (DSP) chips, this reduces computation time. On field-programmable gate arrays (FPGAs), and application-specific integrated circuits (ASICs), this reduces the consumption of hardware resources. This paper presents the results of a study in which three commonly-used functions, i.e. inverse, log, and arctangent functions, have been synthesized for the Xilinx Virtex-II family of FPGAs, using both the RCLT and CORDIC implementations. Each implementation is compared for numerical accuracy of the output, the amount of hardware resources consumed, and throughput latency. In each case, it is shown that an RCLT implementation can be designed to achieve similar mathematical accuracy to the corresponding CORDIC implementation while consuming significantly less programmable logic and with reduced computational delay.

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Report Number
DRDC-OTTAWA-TM-2008-261 — Technical Memorandum
Date of publication
01 Dec 2008
Number of Pages
40
DSTKIM No
CA032274
CANDIS No
531366
Format(s):
Electronic Document(PDF)

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