High-speed parallel I/O FIR filters for FPGAs

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Authors
  1. Low, M.
  2. Lee, J.P.Y.
Corporate Authors
Defence R&D Canada - Ottawa, Ottawa ONT (CAN)
Abstract
Analog-to-digital converters (ADCs) currently available on the market operate at speeds many times faster than those which are possible in the most advanced field-programmable gate arrays (FPGAs). One method of performing real-time filtering is to first demultiplex the serial data stream into m parallel streams, each clocked at a speed m times slower than that of the original serial stream, and then use the FPGA to process the slower parallel streams. A finite-impulse response (FIR) filter which operates on such parallel I/O data can then be architected using a polyphase decomposition technique. This technique has been described in existing literature, but for the cases of m = 8 and m = 16, which are of current practical interest, the governing equations and signal flow diagrams have not been expanded in sufficient detail to allow a hardware designer to rapidly implement the filter in an FPGA. These cases are of interest because they allow filters to be implemented on the most advanced high-speed digitizer boards currently available on the market. Therefore, these non-trivial derivations are explicitly derived in this report, and their architectures are explained through signal flow diagrams. In addition, a number of different FIR filters of various lengths and bus widths were synthesized and placed and routed for the Xilinx Virtex-II Pro XC2VP70 FPGA in order to illustrate the increase in resource consumption between the serial I/O (m = 1) and the m = 8 and m = 16 architectu

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Report Number
DRDC-OTTAWA-TM-2009-204 — Technical Memorandum
Date of publication
01 Jan 2010
Number of Pages
128
DSTKIM No
CA033503
CANDIS No
532793
Format(s):
Electronic Document(PDF)

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