High-speed parallel I/O FFTs for FPGAs

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Authors
  1. Low, M.A.
  2. Lee, J.P.Y.
Corporate Authors
Defence R&D Canada - Ottawa, Ottawa ONT (CAN)
Abstract
Analog-to-digital converters (ADCs) currently available on the market operate at speeds many times faster than those that are possible in the most advanced field-programmable gate arrays (FPGAs). In order to perform real-time fast Fourier transforms (FFTs), the serial data stream must first be demultiplexed into m parallel streams, each clocked at a speed m times slower than that of the original serial stream. An FFT that operates on such parallel I/O data can then be architected using multiple parallel butterfly stages. The parallel-8 (i.e., m = 8) case is of great practical interest because it allows FFTs to operate in real-time on some of the most advanced high-speed digitizer boards currently available on the market. This report describes the architecture and implementation of parallel-8 FFTs in detail, and presents resource consumption statistics for various frame sizes ranging from N = 64 to N = 8192, as implemented for FPGAs in the Xilinx Virtex-II, Virtex-11 Pro, Virtex-4, and Virtex-5 families. A clock speed of 166.667 MHz was achieved, which is sufficient to process data emerging from an ADC clocked at 1.333 GHz in real-time; this is between 3 and 13 times faster than what is possible with the corresponding Xilinx LogiCORE serial architecture. However, the trade-off is that, in the cases examined in this report, the parallel-8 implementation consumes from 1.4 to 9.5 times as many FPGA resources as the corresponding serial implementation.

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Report Number
DRDC-OTTAWA-TM-2010-053 — Technical Memorandum
Date of publication
01 Apr 2010
Number of Pages
86
DSTKIM No
CA034164
CANDIS No
533585
Format(s):
Electronic Document(PDF)

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