ENHANCEMENTS TO THE ELF HARDWARE SYNTHESIS SYSTEM

Authors
  1. Girczyc, E.F.
  2. Elwood, W.L.
  3. Ly, T.A.
  4. Hammerlindl, J.B.
Corporate Authors
Audesyn Inc, Edmonton ALTA (CAN);Chief of Research and Development, Ottawa ONT (CAN) Director of Research and Development Communications and Space
Abstract
The report describes extensions to the Elf verifiable high level synthesis system implemented by Audesyn Incorporated. Also included are summaries of the reports produced on various aspects of verifiable high level synthesis. At the start of this contract, the Elf system was capable of generating circuits to implement algorithms described in a subset of the EV2 programming language. The initial system used several simplifying assumptions which reduced the efficiency of the hardware designed. Further, the software was not interfaced to other CAD tools required to validate (eg. simulators) and complete (eg. autolayout) the design. As part of this contract, Audesyn implemented several major extensions which improve the quality of the circuits generated by Elf. To increase the correctness of circuits generated by Elf, a number of low level issues were identified which must be considered during high level synthesis. TRUNCATED
Report Number
AUTR-89-06 — Technical Report; Contractor Report; See also AUTR-89-06 (DSIS 90-01283) which is a different descriptive report
Date of publication
15 Mar 1989
Number of Pages
150
DSTKIM No
90-01276
CANDIS No
63546
Format(s):
Hardcopy;Originator's fiche received by DSIS

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