IMPLEMENTATION OF FFT AND PULSE COMPRESSION ROUTINES ON THE SPT FREQUENCY DOMAIN ARRAY PROCESSOR

Authors
  1. Behroozi, V.
  2. Damini, A.
Corporate Authors
Defence Research Establishment Ottawa, Ottawa ONT (CAN)
Abstract
The Frequency Domain Array Processor (FDAP) is a VME compatible circuit board built by Signal Processing Technologies (SPT). The FDAP can process integer data arrays containing up to 8192 (32 bit) complex words or 16384 (16 bit) real words. It is capable of 400 Million Operations Per Second (MOPS) with a maximum Input/Output (I/O) rate of four billion bits per second. It also has a double buffered memory architecture permitting I/O transfers to occur in parallel with data processing. The FDAP can be hosted by an IBM PC/AT-compatible computer using a bus adaptor interface available from BIT3 Computer Corp. The FDAP board is based upon SPT's DASP/PAC chip set. This chip set and the various system architectures which can be built around it are reviewed. The FDAP board and its associated development system are also reviewed. The ease of implementation of typical radar signal processing functions on the FDAP board are then examined. TRUNCATED
Report Number
DREO-1041 —
Date of publication
15 Sep 1990
Number of Pages
58
DSTKIM No
91-00545
CANDIS No
67763
Format(s):
Hardcopy;Originator's fiche received by DSIS

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